1. Technical Field
This disclosure relates to integrated circuits, and more particularly, to integrated circuits having on-die networks.
2. Description of the Related Art
The effort to increase the amount of computing power on a single integrated circuit (IC) die has, in recent years, led to the design and manufacture of multi-core processors. A multi-core processor effectively implements two or more processors on a single IC die by providing two or more respective processing cores. Each of the cores may include dedicated cache memories and other circuitry. However, some cache memories may be shared among the cores. Similarly, input/output (I/O) interfaces and other circuitry may also be shared among the cores. System level random access memory (RAM) may also be shared by the cores of a multi-core processor. For various reasons (e.g., maintaining cache coherency, performing parallel computing tasks, etc.), communications may be performed between the various agents (e.g., cores, cache memories, I/O interfaces) of a multi-core processor. In order to support such communications, an on-chip network or a network node may be provided.
An on-die network may be used to connect every agent on the IC die to every other agent. Such an approach may provide efficient communications between a given pair of agents. However, on-die networks may include a large number of interconnections and other logic. In particular, an on-die network may include large numbers of wires, various queues, multiplexers, repeaters, arbitration logic, and so on. This may consume a substantial amount of die area, and may also provide a large number of defect opportunities. Therefore, prior to shipping units of such an IC, extensive testing may be performed to ensure the integrity of the network. If the network does not function properly during such testing, the IC upon which it is implemented may be discarded.